发明名称 WAFER FOR EVALUATING PACKAGE OF SEMICONDUCTOR CIRCUIT AND CHIP EVALUATING DEVICE USING IT
摘要 PROBLEM TO BE SOLVED: To manufacture package evaluating test chips having different sizes from one kind of semiconductor wafer. SOLUTION: On the semiconductor wafer 20, a plurality of single chips 21A, 21B, etc., each has wiring bonding pads 22A1, 22A2, etc., in its circumference and the size required for forming a circuit element. Adjacent wire bonding pads in and out of the single chips are connected to each other so that a daisy chain may be constituted in the wafer 20, and test chips 25 having almost the same size and shape as those of chips used for mass production are cut out from the wafer 20 and formed. COPYRIGHT: (C)2004,JPO
申请公布号 JP2004103639(A) 申请公布日期 2004.04.02
申请号 JP20020259816 申请日期 2002.09.05
申请人 SANYO ELECTRIC CO LTD 发明人 TAMURA HIROYUKI
分类号 H01L21/66;H01L21/56;H01L21/60;H01L21/822;H01L27/04;(IPC1-7):H01L21/66 主分类号 H01L21/66
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