发明名称 |
PLL circuit and data recording controller |
摘要 |
A PLL circuit that optimally generates a clock signal with two reference signals having different frequencies. The PLL circuit includes a VCO for generating the clock signal in accordance with a control voltage. A first loop controls the frequency of the clock signal in accordance with a first reference signal. A second loop controls the phase of the clock signal in accordance with a second reference signal, whose cycle is longer than that of the first reference signal. The second loop supplies the VCO with the control voltage at a constant value until the difference between the frequencies of the first reference and clock signals converges to within a predetermined range. Then, the second loop supplies the VCO with a control voltage at a level corresponding to the difference between the phases of the second reference and clock signals.
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申请公布号 |
US2004062161(A1) |
申请公布日期 |
2004.04.01 |
申请号 |
US20030634151 |
申请日期 |
2003.08.04 |
申请人 |
KIYOSE MASASHI;SHIRAISHI TAKUYA |
发明人 |
KIYOSE MASASHI;SHIRAISHI TAKUYA |
分类号 |
G11B7/0045;G11B7/0037;G11B7/007;G11B20/14;G11B27/19;G11B27/24;H03L7/08;H03L7/087;H03L7/089;H03L7/10;H03L7/107;(IPC1-7):G11B7/00 |
主分类号 |
G11B7/0045 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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