| 摘要 |
The present invention relates to techniques for predicting memory access in a data processing apparatus and particular to a technique for determining whether a data item to be accessed crosses an address boundary and will hence require multiple memory accesses. A data processing apparatus is provided comprising a processor operable to execute instructions upon data items associated with a memory, the memory being arranged to store data delimited by address boundaries, the processor having a plurality of pipeline stages, including a memory access generation stage operable to generate from a memory instruction a memory access for a data item whose address is derived from one or more operands of the memory instruction, and in the event that the address indicates that the data item consists of data on both sides of one of the address boundaries, operable to generate at least two memory accesses to be output sequentially from the memory access generation stage to access the data item at addresses on both sides of the address boundary; prediction logic associated with the memory access generation stage and arranged to receive the one or more operands, to predict from the one or more operands whether the at least two memory accesses may be required to access the data item, and to generate a prediction signal indicative of the prediction; and control logic responsive to the prediction signal indicating that at least two memory accesses may be required to prevent at least the memory access generation stage of the processor from receiving signals from a preceding pipeline stage whilst the at least two memory accesses are being generated. By performing a prediction based upon the operands of the memory instruction instead of waiting for the memory access generation stage to generate a memory access, the prediction logic can generate the prediction signal to enable the control logic to prevent the memory access generation stage from receiving signals from a preceding pipeline stage whilst the address is still being generated. Accordingly, an earlier indication can be provided that at least two memory accesses may be required. Hence, this avoids the critical path which would otherwise present had the generation of the signal had to wait for the address to be generated.
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