发明名称 |
Viterbi decoder and Viterbi decoding method |
摘要 |
In the Viterbi decoder for decoding a trellis-coded modulated signal of this invention, a path memory is constructed of a general RAM, whereby the circuit size and power consumption are reduced. A trace-back section traces back path select signals stored in a trace-back memory by a predetermined length. Using the number of a node through which a most likely path passes obtained by the tracing back and in accordance with a trellis diagram, a subset number generator section outputs coding bits relating to transition to the node concerned and a subset number. A selector section selectively outputs a noncoding bit relating to the transition to the node based on the subset number.
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申请公布号 |
US2004064781(A1) |
申请公布日期 |
2004.04.01 |
申请号 |
US20030673255 |
申请日期 |
2003.09.30 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
KAMADA TAKEHIRO |
分类号 |
H03M13/25;H03M13/41;(IPC1-7):H03M13/03 |
主分类号 |
H03M13/25 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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