发明名称 System and method for limited fanout daisy chaining of cache invalidation requests in a shared-memory multiprocessor system
摘要 A protocol engine is for use in each node of a computer system having a plurality of nodes. Each node includes an interface to a local memory subsystem that stores memory lines of information, a directory, and a memory cache. The directory includes an entry associated with a memory line of information stored in the local memory subsystem. The directory entry includes an identification field for identifying sharer nodes that potentially cache the memory line of information. The identification field has a plurality of bits at associated positions within the identification field. Each respective bit of the identification field is associated with one or more nodes. The protocol engine furthermore sets each bit in the identification field for which the memory line is cached in at least one of the associated nodes. In response to a request for exclusive ownership of a memory line, the protocol engine sends an initial invalidation request to no more than a first predefined number of the nodes associated with set bits in the identification field of the directory entry associated with the memory line.
申请公布号 US2004064653(A1) 申请公布日期 2004.04.01
申请号 US20030672960 申请日期 2003.09.26
申请人 GHARACHORLOO KOUROSH;BARROSO LUIZ A.;STETS ROBERT J.;RAVISHANKAR MOSUR K.;NOWATZYK ANDREAS 发明人 GHARACHORLOO KOUROSH;BARROSO LUIZ A.;STETS ROBERT J.;RAVISHANKAR MOSUR K.;NOWATZYK ANDREAS
分类号 G06F12/08;(IPC1-7):G06F12/00 主分类号 G06F12/08
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