| 摘要 |
<p>An integrated circuit tester and its testing method which enable the preparation of a pattern for minimizing the difference from a pattern generated by a pattern generator and enhances a cut-down ratio of the test cost. A list of all the failures predicted inside a circuit is prepared: for example, one random number pattern is input to determine an in-circuit signal value by logical simulation for the input pattern, resulting in a calculation of controllability, observability, and testability. A target failure the testability of which is minimum is selected out of the list. The route of the target failure is activated with the controllability and observability of the input pattern, and the pattern is so corrected that the reverse number of the input pattern signal value may be minimum. The target failure is processed by failure simulation with a correction pattern: if there is a to-be-detected failure, it is deleted from the failure list.</p> |
