发明名称 |
Information processing apparatus, information processing method, recording medium and program |
摘要 |
The present invention aims at providing efficient bus arbitration. Counters respectively provided for an encoding section and an decoding section are started when there is input of request signal from the respective encoding section and decoding section. The counter values are outputted to respective comparators that compare the counter values with predetermined values to then output the result of comparison to an arbitration controller. The arbitration controller in turn determines priority ranks for the encoding section and the decoding section based on the signals inputted from the comparators and outputs an acknowledgement signal to the module that has the highest priority. The present invention may be applied to LSI's.
|
申请公布号 |
US2004064617(A1) |
申请公布日期 |
2004.04.01 |
申请号 |
US20030663422 |
申请日期 |
2003.09.16 |
申请人 |
SUMIHIRO HIROSHI |
发明人 |
SUMIHIRO HIROSHI |
分类号 |
G06F15/173;G06F13/00;G06F13/362;G06F13/372;G06F15/177;(IPC1-7):G06F13/00 |
主分类号 |
G06F15/173 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|