发明名称 Symmetric voltage follower buffer
摘要 A circuit including a signal input to receive a signal, a buffer circuit to receive the input signal and to generate a buffer circuit output, and a voltage following circuit to receive the signal input and to generate a voltage following output. The buffer circuit output and the voltage following circuit output are coupled to a circuit output node.
申请公布号 US2004061535(A1) 申请公布日期 2004.04.01
申请号 US20030665300 申请日期 2003.09.17
申请人 NAIR RAJENDRAN 发明人 NAIR RAJENDRAN
分类号 H03K19/003;H03K19/0185;(IPC1-7):H03B1/00 主分类号 H03K19/003
代理机构 代理人
主权项
地址