PLL CIRCUIT INCLUDING ANALOG PLL CIRCUIT FOR REDUCING STEADY STATE PHASE ERROR CAUSED BY VARIATIONS AND LEAKAGE

摘要

PURPOSE: A PLL circuit including an analog PLL circuit for reducing a steady state phase error caused by variations and leakage is provided to prevent delay time from fluctuating and being unstable due to jitter though a reference clock signal or a feedback signal contains the jitter. CONSTITUTION: A PLL circuit includes a DLL circuit and an analog PLL circuit. The DLL circuit(2) has a phase difference detector for detecting a phase difference between a reference clock signal and a synchronous clock signal supplied to an electronic circuit which operates in synchronization with the synchronous clock signal, and a phase difference changing unit for outputting a reference clock delay signal and a synchronous clock delay signal in order to increase the detected phase difference between the reference clock signal and the synchronous clock signal. The analog PLL circuit(3) is supplied with the reference clock delay signal and the synchronous clock delay signal from the phase difference changing unit, controls a phase of an output control signal to synchronize the synchronous clock delay signal with the reference clock delay signal, and supplies the output control signal as the synchronous clock signal to the electronic circuit.