| 摘要 |
A method and apparatus for providing a differential clock signal to a plurality of memory modules. In one embodiment, an electronic circuit (e.g. computer system motherboard) includes a clock generating circuit and one or more memory modules. The memory modules may be coupled to receive a differential clock signal from the clock generating circuit via a pair of transmission lines. Each transmission line may be coupled to one of the differential clock inputs on the memory module by a series-connected resistor. Since the differential clock inputs for each memory module are coupled to the transmission lines by series-connected resistors, the changing of the memory module population may have a minimal effect on capacitive loading, and thus delays, than on memory modules where the differential clock inputs are terminated by parallel-connected resistors. |
