| 摘要 |
A phase-locked loop fractional-N frequency synthesizer, particularly of a sigma delta type, has a voltage controlled oscillator, a fractional-N frequency divider, a phase comparator, a charge pump, and a loop filter. The loop filter has a capacitive element for receiving a charge pump current from the charge pump. A filtered charge pump current controls the voltage controlled oscillator. The charge pump is operable in three current modes, a pre-charging/pre-discharging mode, a speed up mode, and a normal, locked mode. In the pre-charging/pre-discharging mode the charge pump is decoupled from the phase comparator so that the phase locked loop is open, and in the speed up and normal modes the charge pump is coupled to the phase comparator so that the phase locked-loop is closed.
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