System and method for clock synchronization of multi-channel baud-rate timing recovery systems

摘要

The circuit has a set of resettable phase error integrators (110) to accumulate proportional outputs until a programmable threshold is reached. A resettable phase error integrator (135) accumulates integrated outputs until another threshold is reached. A set of mod-N integrators (115) generate a frequency and phase corrected clock control signals (120) based on outputs of the phase error integrators. The proportional outputs are generated by a set of amplifiers (105) responsive to inputs (100) from a phase detector. The integrated output (140) is generated by an integrator (130) that integrates output of another amplifier (125) proportional to a frequency offset. An independent claim is also included for an N-channel baud rate timing recovery loop.