Phase-locked loop circuit reducing steady state phase error

摘要

The circuit has a digital locked loop (2) with a phase comparator to detect a phase difference between a reference clock signal (11) and a synchronous clock signal. Reference and synchronous clock delay signals are output with a preset difference by a phase difference changing unit when there is phase difference. An analog phase locked loop circuit (3) is supplied with the delay signals to synchronize the delay signals. The analog PLL supplies an output control signal as the synchronous clock signal to an electronic circuit. An independent claim is also included for a semiconductor integrated circuit.