发明名称 METHOD FOR FORMING ISOLATION LAYER OF SEMICONDUCTOR DEVICE
摘要 PURPOSE: A method for forming an isolation layer of a semiconductor device is provided to avoid a gate bridge in a subsequent process and a self-aligned contact(SAC) fail in a process for forming a landing plug contact(LPC) by eliminating the first nitride layer and a pad oxide layer under the first nitride layer while the first nitride layer is exposed so that the topology in the boundary of an isolation region and an active region is improved. CONSTITUTION: A pad oxide layer and the first nitride layer are formed on a substrate(11). The first nitride layer, the pad oxide layer and the substrate in the isolation region are etched to form a trench. An oxide layer(15), the second nitride layer(17) and an isolation layer(19) are sequentially formed on the resultant structure. The isolation layer is first etched to be planarized by a chemical mechanical polishing(CMP) method using slurry in which a polishing rate of an oxide is 20-200 times as high as a polishing rate of a nitride while the second nitride layer formed on the insulation layer is exposed. The isolation layer, the second nitride layer and the oxide layer are etched by a CMP method using slurry in which a polishing rate of an oxide 2-10 times as high as a polishing rate of a nitride so that the isolation layer is secondly planarized while the first nitride layer is exposed. The first nitride layer and the pad oxide layer are eliminated.
申请公布号 KR20040026239(A) 申请公布日期 2004.03.31
申请号 KR20020057616 申请日期 2002.09.23
申请人 HYNIX SEMICONDUCTOR INC. 发明人 HWANG, EUNG RIM
分类号 H01L21/76;(IPC1-7):H01L21/76 主分类号 H01L21/76
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