发明名称 |
Method for reducing stored patterns for IC test by embedding built-in-self-test circuitry for chip logic into a scan test access port |
摘要 |
A test method and apparatus allows simultaneous loading of multiple scan chains via a single common scan-in port (SDI) and a scan clock signal SCAN CLOCK. Data is scanned into one or more scanpaths from a scan data in (SDI) port under the control of a clock signal, either directly or indirectly through a linear feedback shift register (LFSR). Scan-out data output from the scanpaths may be read at the scan data out (SDO) port, either directly or indirectly through a signature register with optional masking functionality.
|
申请公布号 |
US6715105(B1) |
申请公布日期 |
2004.03.30 |
申请号 |
US20000713517 |
申请日期 |
2000.11.14 |
申请人 |
AGILENT TECHNOLOGIES, INC. |
发明人 |
REARICK JEFF |
分类号 |
G01R31/28;G01R31/3185;G06F11/22;G11C29/48;(IPC1-7):G01R31/28 |
主分类号 |
G01R31/28 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|