发明名称 Hi-speed parallel configuration of programmable logic
摘要 Techniques and circuitry are used to more rapidly configuring programmable integrated circuits. Configuration data is input into a programmable integrated circuit in parallel via parallel inputs (705), and this data is also handled internally in parallel. The configuration data will be stored in a data register (722). This data register is segmented into two or more segments, each segment being made up of a serial chain of registers (808). The configuration data is input into the two of more segments of the data registers in parallel. Circuitry is also provided to handle redundancy.
申请公布号 US6714044(B1) 申请公布日期 2004.03.30
申请号 US20020106673 申请日期 2002.03.25
申请人 发明人
分类号 H03K19/177;(IPC1-7):G06F7/38;G11C19/28 主分类号 H03K19/177
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