发明名称 Method of preventing resist poisoning in dual damascene structures
摘要 A method for forming a dual damascene interconnect in a dielectric layer is provided. Generally, a first aperture is etched in the dielectric. A poison barrier layer is formed over part of the dielectric, which prevents resist poisoning. A patterned mask is formed over the poison barrier layer. A second aperture is etched into the dielectric layer, wherein at least part of the first aperture shares the same area as at least part of the second aperture.
申请公布号 US6713386(B1) 申请公布日期 2004.03.30
申请号 US20010025304 申请日期 2001.12.19
申请人 LSI LOGIC CORPORATION 发明人 HU RONGXIANG;KIM YONGBAE;LEE SANG-YUN;TAKIKAWA HIROAKI;DOU SHUMAY;NEUMAN SARAH;SCHOENBORN PHILIPPE;CHAO KEITH;VIJAY DILIP;ZHANG KAI;EDA MASAICHI
分类号 H01L21/311;H01L21/44;H01L21/4763;H01L21/768;(IPC1-7):H01L21/476 主分类号 H01L21/311
代理机构 代理人
主权项
地址