发明名称 Semiconductor device with high speed latch operation
摘要 A semiconductor device includes a first latch which receives an input signal, and holds the input signal during a half cycle period of a first clock signal, a delay element coupled to an output of the first latch, a second latch which is coupled to an output of the delay element, and holds a signal output from the delay element during a half cycle period of a second clock signal, and a circuit which adjusts at least one of the first clock signal and the second clock signal such that the signal latched by the first latch during the half cycle period of the first clock signal is latched via the delay element by the second latch during the half cycle period of the second clock signal that follows the half cycle period of the first clock signal.
申请公布号 US6714438(B2) 申请公布日期 2004.03.30
申请号 US20020100044 申请日期 2002.03.19
申请人 FUJITSU LIMITED 发明人 KAWABATA KUNINORI
分类号 G11C11/413;G06F1/10;G06F1/12;G11C7/00;G11C7/10;G11C11/407;G11C11/408;H03K3/037;(IPC1-7):G11C11/00;G11C8/00 主分类号 G11C11/413
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