发明名称 Semiconductor memory device having divided word line structure
摘要 A local decoder controlling activation of each word line includes a first transistor connected between first and second nodes, a second transistor connected between a power-supply voltage and the first node, and an inverter driving a word line with the power-supply voltage or a ground voltage in accordance with the voltage of the first node. When a corresponding word line is activated, the second node is set at the ground voltage while the first transistor is turned on. In a burn-in test, a burn-in control circuit forcibly turns off the second transistor in a local decoder corresponding to a word line to be activated.
申请公布号 US6714478(B2) 申请公布日期 2004.03.30
申请号 US20020212816 申请日期 2002.08.07
申请人 RENESAS TECHNOLOGY CORP. 发明人 TOMITA HIDEMOTO;UKITA MOTOMU;OHBAYASHI SHIGEKI;KASHIHARA YOJI
分类号 G01R31/30;G01R31/28;G11C8/14;G11C11/413;G11C29/06;(IPC1-7):G11C8/00 主分类号 G01R31/30
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