发明名称 |
On-chip compression of charge distribution data |
摘要 |
A method and circuit for measuring a charge distribution for readout from a memory such as a FeRAM uses on-chip compression of bit line voltage measurements. One embodiment includes a compression circuit coupled to sense amplifiers. Each sense amplifier compares a series of reference voltages to a corresponding bit line and sets a result value for the comparison. A series of result values from a sense amplifier has a transition when the bit line voltage is approximately equal to the reference voltage. The compression circuit can use the transition as a trigger to record a compressed value indicating the reference voltage at the transition.
|
申请公布号 |
US6714469(B2) |
申请公布日期 |
2004.03.30 |
申请号 |
US20020190370 |
申请日期 |
2002.07.02 |
申请人 |
AGILENT TECHNOLOGIES, INC.;TEXAS INSTRUMENTS, INC. |
发明人 |
RICKES JUERGEN T.;MCADAMS HUGH P. |
分类号 |
G11C7/10;G11C11/22;G11C29/40;G11C29/50;(IPC1-7):G11C29/00;G11C7/00 |
主分类号 |
G11C7/10 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|