| 摘要 |
There are provided a lock detector that does not output a lock detecting signal of incorrect content even when approaching phase synchronization, when an input signal stops suddenly, or when a phase difference becomes zero momentarily in the progress that an output signal is synchronized with an input signal, as well as a PLL circuit including this lock detector. Specifically, a PLL circuit includes a lock detector (20) which comprises a reset signal output part (6, 7, 22 to 24) that outputs a reset signal (Pe) upon a phase difference between an input signal (f1) and a feedback signal (f2); and a D-FF circuit (8) that does not output a lock detecting signal (SL) upon receipt of the reset signal. The feedback signal (f2) is inputted to an NAND circuit (23) such that the reset signal is also based on the signal change of the feedback signal (f2). Further, a counter (21) performing output when the input signal (f1) reaches N-cycle is used for the clock of the D-FF circuit (8).
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