发明名称 PHASE-LOCKED LOOP CIRCUIT
摘要 FIELD: radio engineering. SUBSTANCE: proposed PLL circuit that can be used to generate clock signal for digital processing of video signal coming from television broadcast station has phase comparator, circuit filter, voltage-controlled generator, and cycle counter, as well as prediction window circuit that generates HWIN signal for predicting positions in which REF signals are built up and reference-signal skip compensating circuit that detects loss of REF signal, if any, in HWIN signal and generates high-precision signal d.REFX supplied to voltage-controlled generator to compensate for loss and d.VARX signal to compensate for phase difference between comparison signal VAR and d.REFX signal. EFFECT: enhanced stability of clock signal generated for digital processing of video signal. 19 cl, 22 dwg
申请公布号 RU2226313(C2) 申请公布日期 2004.03.27
申请号 RU20000127100 申请日期 1999.03.31
申请人 发明人 NISIMURA EHJZOU;NAKADZIMA MASAMITI
分类号 H03L7/08;H03L7/085;H03L7/089;H03L7/14;H03L7/191 主分类号 H03L7/08
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