| 摘要 |
PURPOSE: To provide a semiconductor device manufacturing method in which influence of alignment error is reduced. CONSTITUTION: The semiconductor device 10 has a plurality of elements with the same structure composed of a plurality of layers each containing a plurality of the same patterns. With regard to layers 11, 12 to be patterned before the layer 12 is formed that contains such interconnections as to exercise a substantial influence on behavior of the semiconductor device 10 if there is a difference between elements in parasitic capacity values depending on positional relationship with other interconnections, these layers are formed by batch exposure. Thereafter, all other layers 13, 14, 15 to be patterned are patterned by divided exposure.
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