| 摘要 |
PURPOSE: A method for forming a silicide gate line using a semiconductor dual damascene structure is provided to diversify silicide used as a target and reduce silicide resistance by controlling the deposition thickness of an oxide layer in consideration of the thickness of the silicide or controlling the width of a hole etched in an oxide layer etch process. CONSTITUTION: A tunneling oxide layer(2) is deposited on a silicon substrate(1). A nitride layer is deposited on the tunneling oxide layer. After photoresist is formed on the nitride layer, a gate pattern is formed. The nitride layer is etched. After polysilicon(3) is deposited in the hole line of the nitride layer, a chemical mechanical polishing(CMP) process is performed to remove the polysilicon remaining on the nitride layer. After an oxide layer is deposited on a layer on which the CMP process is performed, photoresist is formed to perform a patterning process so that the oxide layer is etched. Polysilicon is deposited in the hole of the oxide layer. The remaining polysilicon on the oxide layer is eliminated. A gate pattern formation process is performed to form a final gate line. A sidewall deposition process and an etch process are performed to form a sidewall nitride layer(4) on the gate line. After the oxide layer on the polysilicon is removed, a silicide material is deposited in the space from which the oxide layer is removed. After an annealing process is performed to form final silicide, a cleaning process is performed to eliminate unreacted silicide.
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