SEMICONDUCTOR STORAGE DEVICE

摘要

PROBLEM TO BE SOLVED: To correctly detect sense timing regardless of an array configuration.

SOLUTION: Dummy circuits (1a to 1c) having a plurality of dummy cells are provided for each of the prescribed number of word lines. When a corresponding word line is selected, the plurality of dummy cells included in the dummy circuits are used to drive a dummy bit line (DBL) having the same load as a normal bit line does. A dummy sense amplifier (DSA) detects the potential of the dummy bit line (DBL) to generate a sense enable signal (SE).

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