发明名称 |
METHOD AND DEVICE FOR VERIFYING DIGITAL CIRCUITS |
摘要 |
The aim of the invention is to verify digital circuits that have, in particular, multiplying structures. To this end, an equivalency test between the digital circuit (6) and a reference description (5) of this digital circuit is performed in such a manner that, firstly, the realized implementation alternative of a number of predetermined different implementation alternatives (7) is determined for the multiplying structures implemented in the digital circuit (6) and is used in the reference description (5) instead of the respective multiplication function in order to subsequently carry out the equivalency test with the consequently modified reference description. This enables a considerable increase in the structural match between the reference description and the digital circuit to be verified thus resulting in an overall acceleration of the verification method. |
申请公布号 |
WO2004025520(A2) |
申请公布日期 |
2004.03.25 |
申请号 |
WO2003EP09179 |
申请日期 |
2003.08.19 |
申请人 |
INFINEON TECHNOLOGIES AG;HOERETH, STEFAN;MUELLER-BRAHMS, MARTIN;RUDLOF, THOMAS |
发明人 |
HOERETH, STEFAN;MUELLER-BRAHMS, MARTIN;RUDLOF, THOMAS |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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