Multipurpose architecture and method for testing electronic logic and memory devices

摘要

A logic device test system having memory device testing capabilities includes vector storage memory which receives and stores test vectors from a system controller. An address sequencer controls retrieval of the test vectors from the vector storage memory. Data driver circuitry coupled to the vector storage memory receives the test vectors retrieved from the vector storage memory. The data driver circuitry further includes data drivers coupleable to and driving devices under test using the test vectors. The data driver circuitry further including driver formatting circuitry coupled to the data drivers and formatting test vectors provided to the data drivers. A plurality of format code save registers in the driver formatting circuitry save test vectors and selectively provide the test vectors to the data drivers for driving the devices under test.