| 摘要 |
First, second, third and fourth inverters are serially connected to form an inverter chain. The first inverter receives a clock input. A first current source is connected to the power supply side of the first inverter. A second current source is connected to the ground side of the third inverter. If the duty ratio of a clock output is lower than a desired value, the magnitude of an electric current in the first current source is decreased such that the falling timing of the clock output is delayed. If the duty ratio of the clock output is higher than a desired value, the magnitude of an electric current in the second current source is decreased such that the rising timing of the clock output is delayed. With such an arrangement, the margins of the setup time and hold time between the clock and data are readily secured.
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