| 发明名称 |
Generation of refined switching windows in static timing analysis |
| 摘要 |
A method and structure to determine timing windows in a static timing analysis of an integrated circuit design, determines for at least one node in the integrated circuit design, an initial set of sub-windows and merges the sub-windows of the initial set into a final set of sub-windows.
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| 申请公布号 |
US2004060022(A1) |
申请公布日期 |
2004.03.25 |
| 申请号 |
US20030667083 |
申请日期 |
2003.09.18 |
| 申请人 |
ALLEN ROBERT J.;ARUNACHALAM RAVISHANKAR;HATHAWAY DAVID J. |
发明人 |
ALLEN ROBERT J.;ARUNACHALAM RAVISHANKAR;HATHAWAY DAVID J. |
| 分类号 |
G06F17/50;(IPC1-7):G06F9/45 |
主分类号 |
G06F17/50 |
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