| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a ΔΣ modulator which is excellent in spurious characteristics and in which power consumption can be reduced and the scale of a circuit can be reduced, and to provide a PLL circuit in a ΔΣ modulation method. <P>SOLUTION: The ΔΣ modulator 6a has a multiplier 11 to multiply a first setting value and a feedback signal, a first adder 12 to add a second setting value to an output signal of the multiplier 11, a first integrator 13 to integrate an output signal of the first adder 12, a second integrator 14 to integrate an output signal of the first integrator 13, a second adder 15 to add both output signals of the first/second integrators 13, 14, and a comparator 16 to compare an output signal of the second adder 15 with a value correlative to the first setting value and to output three values showing comparison results as the feedback signal. A division ratio of a divider 2 in the PLL circuit in the ΔΣ modulation method can be set to three types since the output of the comparator 16 in the ΔΣ modulator 6a is made to be the three values. It is possible to prevent spuriousness from occurring since a changing cycle of a division ratio can be set longer than that of the conventional one. <P>COPYRIGHT: (C)2004,JPO |
