| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a low skew clock distribution circuit in which the number of pins in an LSI is decreased and a chip area is reduced. <P>SOLUTION: A low skew clock distribution circuit (10) is provided with a PLL circuit (7) and an LSI (11). The PLL circuit (7) is connected to (n) ((n) is a positive number) general ICs (8-1 to 8-n). The LSI (11) outputs a reference clock (RCK) and a feedback clock (FCK2) to the PLL circuit (7). The PLL circuit (7) distributes out the reference clock (RCK) from the LSI (11) to the (n) general IC (8-1 to 8-n), and outputs the feedback clock (FCK2) from the LSI (11) to the LSI (11). The reference clock (RCK) outputted from the PLL circuit (7) to the (n) general ICs (8-1 to 8-n) is used as a clock to the (n) general ICs (8-1 to 8-n). <P>COPYRIGHT: (C)2004,JPO |
