| 摘要 |
PROBLEM TO BE SOLVED: To obtain a semiconductor integrated circuit capable of performing stable scanning tests by preventing the data from being slipping out due to the the flip-flop holding time fault caused by a clock skew. SOLUTION: A scanning test of a combination circuit 200 is performed on the basis of a test pattern generated by a scan pattern generation circuit 300, a comparison control circuit 400 compares a test result with an expected value to check the shifting of the flip-flops 100-105. When the slip of the data is generated due to the hold time fault caused by a clock skew and non-coincidence between the test result and the expected value is generated, the circuit 400 specifies the generated position of the data slip and controls the clock delay by a control signal for a delay control selector. Then the test pattern is inputted from a scanning-in signal SI to perform the scanning test of the combination circuit 200. COPYRIGHT: (C)2004,JPO
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