| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit and its testing method and device capable of accomplishing an effective test of the integrated circuit and generating a scan design involving less entanglement of the wiring. SOLUTION: In the scan distribution compression mode, a test pattern is supplied from supply terminals 301-30N to scan chains 201-20N provided at stages. The test result data accommodated in the scan chain is compressed by a MISR 110 at each stage. In the signature reading mode, the signature read out of the MISR 110 at each stage is compressed bit for bit by exclusive logical sum circuit 131-13N and emitted. In the sequential scan mode, the scan chains 201-20N at each stage are connected in series to constitute N pieces of scan chains. COPYRIGHT: (C)2004,JPO
|
