| 摘要 |
A data synchronization cell is provided that comprises first and second synchronizers that are generally adjacent one another and that have their M1/S1 clock ports tied together. The result is that both synchronizers are driven by the same clock signal, which arrives substantially simultaneously at the M1/S1 clock ports of the synchronizers due to the fact that the synchronizers are side-by-side and their respective M1/S1 clock lines are tied together. Because the first and second synchronizers of the present invention are adjacent one another and have their respective M1/S1 clock lines tied together, clock skew is negligible and thus no buffer is needed between the synchronizers, which increases the amount of time allowed for resolution, reduces or eliminates the possibility of hold time violations occurring, and reduces the amount of area required to instantiate the synchronization cell.
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