| 摘要 |
A bit position synchronizer including a sampling circuit which samples an input signal based on a plurality of phases of clock signals to obtain a plurality of sampled signals, a selector which selects one of the plurality of sampled signals, each of which is delayed for a short period, based on a selection signal and which outputs an output signal, a detection circuit which detects a first changing point and a second changing point of the sampled signals, a first register which stores a first value for the first changing point, a second register which stores a second value for the second changing point and a third register which stores an intermediate value between the first and second values and which outputs the selection signal.
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