发明名称 |
Host memory interface for a parallel processor |
摘要 |
A memory interface for a parallel processor which has an array of processing elements and can receive a memory address and supply the memory address to a memory connected to the processing elements. The processing elements transfer data to and from the memory at the memory address. The memory interface can connect to a host configured to access data in a conventional SDRAM memory device so that the host can access data in the memory.
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申请公布号 |
US2004054844(A1) |
申请公布日期 |
2004.03.18 |
申请号 |
US20030395695 |
申请日期 |
2003.03.20 |
申请人 |
KIRSCH GRAHAM |
发明人 |
KIRSCH GRAHAM |
分类号 |
G06F12/00;G06F13/42;G06F15/78;G11C7/10;(IPC1-7):G06F12/00 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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