WORD AND BIT LINE ARRANGEMENT FOR A FINFET SEMICONDUCTOR MEMORY

摘要

The invention relates to a semiconductor memory having a plurality of interspaced ribs (FIN) made of a semiconductor material, wherein a plurality of channel areas and contact areas (S/D) are configured in each of the ribs (FIN); a plurality of word lines (WL); a plurality of memory layers (14), wherein at least one of the memory layers (14) is arranged between each of the channel areas and the word line (WL), and a plurality of bit lines (BL), wherein the longitudinal axis of the first bit line sections (22) extend parallel to a first ((BL1)) bit line direction and the longitudinal axis of the second bit line section (24) extends parallel to a second ((BL2)) bit line direction, wherein the second bit line direction ((BL2)) is twisted relative to the first bit line direction ((BL1)) and each of the bit lines (BL) is electrically connected to a plurality of contact areas (S/D), wherein a contact area (S/D) that is not connected to a bit line (BL) is arranged between two contact areas (S/D) of the same rib (FIN) that are connected to one of the bit lines (BL),