| 摘要 |
PROBLEM TO BE SOLVED: To provide a method for designing a semiconductor integrated circuit in which a test circuit can be incorporated without increasing the quantity of wiring, a design load can be minimized by suppressing an increase in circuit area while ensuring required performance easily, and the period of development can be shortened. SOLUTION: A single chip circuit is designed with a function required for actual operation in the initial stage of design (floor plan stage), and a floor plan is effected based on circuit information and the information of a function block IP core, and the like, requiring the verification of a single chip function. When a physical layout is effected, the incorporation of the function block IP core and a required test circuit is examined so that circuit hierarchy is blocked depending on the physical layout. COPYRIGHT: (C)2004,JPO
|
