TEST STRUCTURES FOR ELECTRICAL LINEWIDTH MEASUREMENT AND PROCESSES FOR THEIR FORMATION

摘要

In a method of determining a linewidth of a polysilicon line (16) formed by a lithographic process, a polysilicon layer is formed on a substrate. A line (16) is patterned from said polysilicon layer using said lithographic process and a Van der Pauw structure (14) is patterned from said polysilicon layer. N>2< is then implanted into the polysilicon line (16) and the polysilicion Van der Pauw structure (14) to form a depletion barrier. A P-type dopant is the implanted into the polysilicon line (16) and the polysilicon Van der Pauw structure (14) and the dopant is activated. A sheet resistivity of the Van der Pauw structure (14) is determined, and the linewidth of the polysilicon line (16) is then determined by electrical linewidth measurement using the sheet resistivity of the Van der Pauw structure (14) as the sheet resistivity of the polysilicon line (16). A related test structure is also disclosed.