发明名称 Digital circuit verification method, especially for verification of multiplication structure containing circuits, in which a reference circuit is first matched to the circuit to be verified to speed the verification process
摘要 Method for verifying digital circuits, whereby a digital circuit (6) that is to be verified is compared with a reference description (5) so that by use of equivalence testing errors can be detected in the digital circuit. Accordingly, from a number of different possible circuit implementations (7), the one that most closely matches with the circuit to be verified is selected and used to replace the reference circuit. Lastly equivalence testing takes place between the selected circuit and the digital circuit to be verified. Independent claims are included for; (1) a device for verification of digital circuits; (2) computer program; and (3) implementation of the method.
申请公布号 DE10239782(A1) 申请公布日期 2004.03.18
申请号 DE20021039782 申请日期 2002.08.29
申请人 INFINEON TECHNOLOGIES AG 发明人 HOERETH, STEFAN;MUELLER-BRAHMS, MARTIN;RUDLOF, THOMAS
分类号 G06F17/50;(IPC1-7):G06F17/50;G06F7/02;G06F9/455 主分类号 G06F17/50
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