| 摘要 |
<P>PROBLEM TO BE SOLVED: To improve the reliability by skew reduction between bits of readout data. <P>SOLUTION: A wiring path of a timing control signal 11 input to a memory circuit block 20 of a short data readout time (close to a data output terminal) has wirings 30 to 31, which are extended linearly from a data output terminal 4 to an opposite side and looped back near the farthermost memory circuit block 20. Turning over is repeated, in accordance with the number of arrangements of the memory circuit blocks 20 also to a branch wiring branched from the turned over wirings 30 to 31, and the wiring is connected to the memory circuit block 20 near the repeated turned over wiring. Thereby, the sum of the wiring lengths of a data readout paths and the wiring lengths of a timing signal input paths with respect to all the memory circuit blocks 20 is made equal. <P>COPYRIGHT: (C)2004,JPO |
