| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a microcontroller for performing the transition of an operation mode between a extremely low speed mode and a normal operation mode without losing immediacy. <P>SOLUTION: When the extremely low speed mode is specified during the normal operation mode, a value corresponding to a clock mode specifying register 105 is set. Thereby, a clock control circuit makes a clock frequency into a extremely low speed frequency and a DRAM 102 is operated in a self-refresh mode. The DRAM receives a signal showing the completion of the transition into the mode and then a remap control circuit controls an address change circuit 114 so that the control of a program is transferred from the DRAM to a region of a ROM 103. When the reset to the normal operation mode is instructed during the extremely low speed mode with interrupting operation, an interruption control circuit 116 changes a value for the clock mode specifying register, resulting in reset to a frequency for the normal mode and in the transition of an address space from the ROM to the DRAM. <P>COPYRIGHT: (C)2004,JPO</p> |
