发明名称 |
Method of manufacturing electronic device |
摘要 |
In a method of forming a circuit pattern including fine pattern features and fine space, a hard mask layer is patterned with a first pattern defined by eliminating the fine space for merging the pattern features. Thereafter the hard mask layer is shrank. Next, the hard mask layer is patterned with a second pattern that is defined on the basis of the fine space. Finally, the circuit pattern is formed in an underlying layer using the hard mask layer as a mask.
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申请公布号 |
US2004054981(A1) |
申请公布日期 |
2004.03.18 |
申请号 |
US20030360860 |
申请日期 |
2003.02.10 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
OKAGAWA TAKASHI;YAMADA TETSUYA;UENO ATSUSHI;YAMAGUCHI ATSUMI;TSUJITA KOUICHIROU |
分类号 |
G03F7/40;G03F7/00;G06F17/50;H01L21/027;H01L21/033;H01L21/28;H01L21/31;H01L21/3213;(IPC1-7):G06F17/50 |
主分类号 |
G03F7/40 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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