发明名称 Viterbi decoder
摘要 Two registers R2 and R3 are used as input operands. The upper and lower sides of the register R2 are compared, and a value selected in accordance with the comparison result is stored on the upper side of another register R4. The upper and lower sides of the register R3 are compared, and a value selected in accordance with the comparison result is stored on the lower side of the register R4. Data on the upper and lower sides of the register R4 are simultaneously read out and stored at adjacent addresses in a memory (16) via a 2-word width bus (17) or bus (18).
申请公布号 US2004054958(A1) 申请公布日期 2004.03.18
申请号 US20030466302 申请日期 2003.07.15
申请人 IKEKAWA MASAO 发明人 IKEKAWA MASAO
分类号 G06F11/10;H03M13/41;H04L1/00;(IPC1-7):H03M13/03 主分类号 G06F11/10
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