METHOD FOR CHECKING AN INTEGRATED CIRCUIT FOR ELECTROSTATIC DISCHARGE ROBUSTNESS
摘要
The invention is a method and a computer program product for checking an integrated circuit for electrostatic discharge (ESD) robustness at the design level and comprises essentially the check of the layout of the integrated circuit against a set of rules defining one or more transistor geometric and/or electrical and/or material values and generating an output or report of this check. This method can check automatically a complete IC design layout at any design level. An exemplary design is an ESD protection layout, a design block or a complete IC design.
申请公布号
WO2004023350(A2)
申请公布日期
2004.03.18
申请号
WO2003IB03787
申请日期
2003.08.25
申请人
KONINKLIJKE PHILIPS ELECTRONICS N.V.;KEMPER, WOLFGANG;MRCARICA, ZELJKO;KELLER, THOMAS;THOMMEN, DANIEL;REINER, JOACHIM, CHRISTIAN
发明人
KEMPER, WOLFGANG;MRCARICA, ZELJKO;KELLER, THOMAS;THOMMEN, DANIEL;REINER, JOACHIM, CHRISTIAN