发明名称 Connection and build-up-process for multi-chip-modules
摘要 <p>Preparation of a multichip-module has a series of layers of dielectric material with embedded conductors. The dielectric material is temperature stable, base-resistant polymer having a dielectric contact of 3 or less on a non-conductive base. It forms a boundary edge for currentless, autocatalytic production of conductor paths. The dielectric material is provided with a layer of organic solvent soluble material (lift-off layer). The dielectric material and lift-off layer are structured in a lithographic step, using ether direct or indirect structuring and forming trenches in the dielectric material having an aspect ratio of 1 or more. A metallic seed layer is formed by evaporation. The lift-off layer is removed using an organic solvent and conductor paths are formed in the trenches by currentless metal deposition. <IMAGE></p>
申请公布号 EP0690494(B1) 申请公布日期 2004.03.17
申请号 EP19950109271 申请日期 1995.06.14
申请人 INFINEON TECHNOLOGIES AG 发明人 LEUSCHNER, RAINER, DR.;AHNE, HELLMUT, DR.;BIRKLE, SIEGFRIED, DR.;HAMMERSCHMIDT, ALBERT, DR.;SEZI, RECAI, DR.;NOLL, TOBIAS, PROF. DR.;DUMOULIN, ANN, DR.
分类号 G03F7/075;C23C14/20;G03F7/26;H01L21/48;H05K3/00;H05K3/02;H05K3/04;H05K3/10;H05K3/18;H05K3/38;H05K3/46;(IPC1-7):H01L21/768;H01L23/52 主分类号 G03F7/075
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