发明名称 VECTOR LOGIC TECHNIQUES FOR MULTILEVEL MINIMIZATION
摘要 <p>Very complex, multilevel, logical expressions are represented in vector format (step 1). The logical is simplified by identifying opposing couples, a literal and its negation, and replacing symmetrical logic expressions attached to the opposing couples with a single version. (Term 1, Term 2, Term3).</p>
申请公布号 WO2004023351(A1) 申请公布日期 2004.03.18
申请号 WO2003US27955 申请日期 2003.09.05
申请人 WESTPHAL, JONATHAN 发明人 WESTPHAL, JONATHAN
分类号 G06F17/50;(IPC1-7):G06F17/50;G06F17/60 主分类号 G06F17/50
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