Method and apparatus for measuring the quality of delay test patterns

摘要

A method and apparatus are provided for determining quality metrics associated with a test pattern used to test an integrated circuit (IC). The delays associated with (1) a longest sensitizable path through the IC that includes the delay fault and (2) an actual path exercised by the test pattern through the IC that includes the delay fault are determined. A difference between the delays is then obtained. The difference is then combined with a difference between a speed at which the test is performed and a design specification operating speed of the IC for the actual path. The sum represents the first quality metric associated with the test pattern for a given fault site. The ratio of the delays of the actual path to the longest sensitizable path represents the second quality metric associated with the test pattern for a given fault site. The metrics for the individual fault sites can be statistically combined into respective metrics at the IC level to assess the quality of a single test pattern or for a group of test patterns.