| 摘要 |
A clock generating circuit and method thereof is provided. The frequency ratio between the output clock and the system clock is calculated as that the first preset value divides by the second preset value. A data value is stored into a register. The sum of the data value and the first preset value is calculated as a first result by the first adder. The sum of the first result and the second preset value is calculated as a second result by the second adder. A multiplexer (MUX) is used to select the data value that should be stored into the register at next system clock from the first result and the second result according to the level of the output clock. The first result is compared with a reference value by the first comparator to generate the output clock, so that the frequency of the output clock can be changed arbitrarily and it is not required to redesign the circuit.
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