发明名称 |
Method for multi-threshold voltage CMOS process optimization |
摘要 |
A method for multi-threshold voltage CMOS process optimization. The method includes the steps of: providing a semiconductor substrate with a plurality of devices of different threshold voltages; establishing a plurality of types of timing models for a timing calculation; obtaining a static timing analysis report through the timing calculation; defining a large and a small setup time margin as a Tl and a Ts; changing the devices whose setup time margins are less than Ts to low threshold devices; changing the devices whose setup time margins are greater than Tl to high threshold devices; checking a setup time of each device; changing the devices whose setup time margin does not meet the enhanced static timing analysis report; performing a first pocket implant process for the normal threshold devices; performing a second pocket implant process for the low threshold devices and performing a third pocket implant process for the high threshold devices.
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申请公布号 |
US6708312(B1) |
申请公布日期 |
2004.03.16 |
申请号 |
US20020225284 |
申请日期 |
2002.08.22 |
申请人 |
SILICON INTEGRATED SYSTEMS CORP. |
发明人 |
CHIANG MING-MAO;SHIH CHING-CHANG;TSAI CHIN-CHO;LIU TIEN-YUEH;HUANG KUO-CHUNG |
分类号 |
G06F17/50;H01L21/66;H01L21/8238;(IPC1-7):A06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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